COONTEC, Soongsil University build LLM-based Power ISA verification pipeline

COONTEC and Soongsil University are jointly developing a Power Instruction Set Architecture verification system that links structured reference data, LLM-generated code, and formal and execution-based checks. The project aims to reduce errors in emulator development and create a traceable workflow from specification to build integration.

Why it matters: - Power ISA emulators are hard to build because engineers must translate long specifications into correct code. - The COONTEC-Soongsil University pipeline is designed to reduce interpretation errors and make verification traceable from source documents to compiled output. - The project could improve how virtualization teams validate instruction behavior before moving to hardware-level testing.

What happened: - COONTEC said it is jointly developing a Power ISA Verification System with Soongsil University. - The system uses a multi-stage pipeline that structures Power ISA specifications, generates candidate Instruction Set Simulator C code with an LLM, and verifies the result step by step. - The announcement was made Aug. 11, 2026, in Seongnam, Gyeonggi-do, South Korea.

The details: - The pipeline extracts instruction definitions and related information from the Power ISA manual. - The structured Ground Truth database includes mnemonics, opcodes, operands, bit fields, pseudocode, special registers, flags and instruction descriptions. - The database acts as a reference layer between the original specification and the generated implementation. - Retrieval-augmented generation is used so the LLM can reference both the structured database and the source documents. - The system generates candidate ISS C code for a virtual machine and then routes that code into separate review and verification stages. - A web-based dashboard supports specification lookup, source code review, verification tasks and result checking. - The dashboard is intended to let users trace each instruction through the pipeline. - Formal verification uses the Z3 SMT solver for instructions that can be represented symbolically. - The team compares mathematical representations from the specification and the generated code across operation results, state information, conditional processing and bit-field behavior. - Instructions that are difficult to express formally get execution-based verification using representative inputs and trusted software references. - Generated-code results are compared with reference results to check whether behavior matches. - The team is integrating generated code into the virtual machine source tree and compiling it to surface syntax errors, ISS API compatibility issues, and type and dependency problems. - PowerPC build integration is currently in progress. - Full end-to-end verification is a later development phase. - The company’s website is More information. - COONTEC’s social links include LinkedIn, Instagram, Facebook, YouTube and X.

Between the lines: - The project blends LLM generation with formal methods, which suggests the team is trying to control hallucinations and spec drift rather than trust model output directly. - The workflow also creates an audit trail that can show where a mismatch enters the process, from reference data to compiled behavior. - Future hardware-based checks will matter because software-reference verification alone may not catch every edge case in real systems.

What's next: - The research team plans to cross-check the structured reference data against multiple independent machine-readable references. - PowerPC build integration is expected to continue. - The team plans to expand execution tracing so register, memory and state information can be compared at the instruction level. - Future verification will include Golden Logs from physical reference hardware, trusted compilers and execution environments, and validated implementations. - Verification results will be fed back into code generation, with expert review added when needed. - COONTEC CEO Joon Pang said the company plans to expand verification to physical hardware and Golden Logs in later stages to improve virtualization development and verification efficiency.

The bottom line: - COONTEC and Soongsil University are building a verification pipeline meant to connect specification, code generation, compilation and validation in one trackable system, with hardware-backed testing still ahead.